Sound Mover - Marc Marc V8 Filter Unit Data Interface Write timing Read cycle DAC VOICES Power Supply In 1995 the V8 computer controllable 8 channel filter unit was add to the Sound Moving Installation. By this not only moving of the sounds was possible but also, at the same time, dynamic timbre changes. For the filters I took out the filter board from my CTS 2000 synthesizer keyboard (which I did not use anymore). This board count 8 analog Low Pass filters with controllable Frequency, Resonance, Volume and output Balance parameters. It is also possible to use each filter as a Sine Wave generator. On board already a 12 bit DAC, Sample & Hold and Demultiplexer was available. To use this filter board independently from its originally processor based system, I designed a data interface to have the filters controlled by the same Atari ST computer that also controls the SM132 sound mover unit. Back to Sound Mover block diagram Like the SM132 unit, the V8 unit is MIDI controlled but also controllable by a parallel port. In practice both the SM132 and V8 unit are MIDI controlled to guarantee that both units are galvanic insulated from each other and the computer. At this moment the 8 filter inputs are mixed to a stereo output (based on the original board lay out) but, in the future this will be modified to create separated outputs for each filter which then allows a more flexible use of the filters. Most of the projects that were done with the sound moving system used Noise as a base signal to be colored in one way or another and then moved over the 16 loudspeaker system in sense of a sound choreography. Since the V8 unit is operational the Noise signal is fed to the filters and then simultaneous with the geography controlled in timbre. Each of the two output channels of the filter unit has simultaneous filters to color the noise signal. By varying the parameters of the filters two multi timbral structures can be created. These two sound structures can be patched in such way to the SM132 unit that both signals have 16 VCA's available to be independently moved over the 16 loudspeaker system. By software control it is also possible to create more than 2 moving signals. Although there could be only two timbre structures, it is possible to create a maximum of 16 moves - each using 2 channels. The explanation on the electronics are quite exhausting and even this does not give you all the details and aspects about the design. You are expected to know already about electronic principles more than a bit. Although the worksheets able you to copy the unit this does not mean that my explanation was intended to help you with this. I simply do some serious lalalala about it to stimulate designing electronics as an Art (versus manufacturer application imitation)

 

. . . The Job First lets see what exactly the job is that the interface must handle. Each of the 32 parameters that the filter unit counts is a 12 bit value. Thus the 8 bit memory counts 2 bytes for each parameter (divided into a 7 High bits and 5 Low bits). Besides receiving first the High bits and then - in the same data string - followed by the Low bits, the data protocol logic also need to have the intelligence to receive only the LOW or HIGH bits of the 12 bits value. This is to reduce the amount of data that need to be send by the computer (sending data by MIDI interface has a limited speed and during sending data the Atarai ST computer can not do any other task). Between each data byte which the interface receives it needs to refresh all of the 32 analog memories by fetching the data from the RAM memory, converting it into an analog value and then sending it via the demultiplexer to the sample and Hold circuitry to refresh the analog memory (this needs to be done 32 times within 32 Milliseconds). The big advantage of hardware design above a software controlled micro processor system is the fact that the signals in pure hardware design can operate parallel at the same time. In contrast: a processor only can handle one instruction at a time and thus operates serial. Data protocol Principally this looks like this: 240+ID, Parameter address, Parameter value. First the start byte of a data sequence needs to be sends. Like the SM132 this is 240 plus the ID add to it (0...15). Of course the V8 unit has another ID than the SM132. Then the parameter address is send (0...31). The highest bit of this address byte determines how the next data byte(s) will be treated (and this is the intelligence that was mentioned above). When the high bit is set, the interface treats the next byte as being the 7 High bits of the 12 bits value, otherwise this next byte will be treated as the 5 low bits of the 12 bits value. When this next byte would be defined as the 7 high bits it is possible to send the 5 low bits immediately behind it to complete the 12 bits value but, this is not necessary (it is allowed to not complete the data stream without any effect for the next data stream). Thus, the following data streams (formats) are possible: Start byte, Address byte, High byte, Low byte Start byte, Address byte, High byte Start byte, Address byte, Low byte, High byte Start byte, Address byte, Low byte Start byte, Address byte Start byte The advantage is clear: flexibility in data format to optimize the software and insensitivity to data errors over a longer period (each start byte resets the logic circuitry). MIDI/Parallel switch The double throw switch, that can be seen in the diagram. serves the function to switch from MIDI to parallel control. One side of the switch selects the STROBE input and the other side controls which incoming data lines are used. How the data format is realized An incoming start byte is recognized by the fact that the number is 240 or higher (up to 255). This is done by the ID DETECTOR (74HC688). It compares each incoming byte with a preset value and when they are the same it makes its P=Q output low (telling that it was the ID that came in). Also, when the value 240 is seen (thus without the ID additive) also the 4NAND gate N5 will be generate a low level. These two detected levels initialize the ID AND CYCLE PROCC. That not only the exclusive ID of the V8 unit is detected but also the value 240, which is the base value of the start byte, has to do with the fact that it must be recognized when another unit on the same MIDI line but with different ID is sending data. Because the data format allows a non static amount a bytes it must be prevented that data that is send for another unit will be seen by the V8 unit as valid. The 240 detector prevents this because it resets the CYCLE logic at each incoming 240 value. Start byte The start byte with the correct ID however also starts via N2: the CYCLE logic (74HC194). The Strobe pulse that comes with the start byte has no effect on the CYCLE logic because it is suppressed by the fact that also a reset pulse is active at the same time. After the start byte with correct ID initialized the CYCLE logic it is ready to respond to the next byte which will be the address and its high bit definition to decide how to treat the coming value byte afterwards. Address byte When the address byte arrives the strobe pulse will cause the Q0 output of the HC194 to turn high. This will activate the ACTR REG (74HC574) to latch in the address to be memorized. At the same time the high bit (d7) of the address is fed to the data Flip Flop III and clocked in. This high bit appears at the Q output of FF-III and its complementary level at the NOT(Q) output. These two outputs are connected to FF-VII and FF-VIII to serve as the determining logic on how to treat the value byte(s) yet to come. Value byte When the value byte arrives the strobe pulse will set the Q1 output of the HC194 high. FF-VII will be clocked to transfer its data input (the high/low byte definition bit of the address byte which was stored by FF-III) to its Q and NOT(Q) output. When it is a high level it will go via de diode to the NOR gate N10 to set the RAM A0 address line low via NOR gate N10 which means that RAM address mode is settled for receiving the High byte of the 12 bit value. At the same time the Q1 output of the HC194 will be fed to the RC7 network to generate via the NOR gate N3 a low pulse that will disable the demultiplexer decoder logic. At this point the refresh actions for the analog memories are stopped. The low pulse from N3 also will generate a positive pulse via NOR gate 4. This will inhibit the demultiplex clock generator and, at the same time, will clock the DCTR REG (HC574) to latch in the value byte. By the time that the value is settled stable in the latch FF-I has been clocked and at its complementary outputs will change levels. The NOT(Q) output will enable both the DCTR and ACTR latches by making the OE input low and thus both value byte and address byte will be put at the internal bus that interfaces with the RAM memory. At the same time the Q output of FF-I has disconnected the refresh address register RDCTR from the internal address bus and also switched the RAM to the write mode (data input mode) by making the NOT(OE) pin high. Write pulse By the time that these steps are settled with stable levels FF-II is clocked to generate a short write pulse at the NOT(WE) input pin of the RAM. A fraction later the NOT(CS) input of the RAM is made low via NOR gate N9. This enables the RAM and the value byte will be stored into the RAM. The time duration of the write pulse is determined by RC3. As you can see the capacitor of this network is drawn stippled - simply because this capacitor is not a individual component add to the board but the sum of the internal capacities of the NOT(reset) inputs from FF-II, I, VII and VIII. This total capacity will be large enough to generate a long enough write pulse duration with a save margin. Because the reset input of these four FF's are tied together they all will be reset after the falling edge of the write pulse. The outputs of FF-II then will follow by changing levels again. Next value byte At this point the write cycle is completed and the system goes back into the read status. A short dead time will follow (until the time duration of the pulse from N3 has passed which is determined by the RC7 network at the input of N3). Then the GATED CK OSC is started again and the refreshing actions continues. In the mean time the next data byte is on its way (busy to be converted from serial to parallel). When this next value byte arrives the strobe pulse will make the Q2 output of the HC194 high and the same write procedure, as just was described, follows but the difference may lay in the fact that instead of a high byte a low byte will be stored. This is, like already mentioned, determined by the level that was stored into FF-III and appears on the outputs of FF-VII and FF-VIII. When the high bit of the address bytes was set high, as described before, it is transferred to FF-VII when the first value byte appears. When the second value byte appears, the complement of the high bit is transferred by FF-VIII. This will be a low level and thus will keep the RAM A0 address line into the low byte modus. Actually this is not caused by any action because the low level at the Q output of FF-VIII already was there since the reset of the previous write cycle. You might wonder why FF-VIII is there. There are two reasons. The first one is to fulfill the task to send the low byte before the high byte. In this case the high bit of the address byte need to be set low and will be transferred via the NOT(Q) output of FF-III as a high level which on its turn will appear as a high level at the Q output of FF-VIII when the second value byte arrives. In this case FF-VIII becomes active. But, is it any use to first send the low byte and then the high byte? At the moment not but, because the FF chips count two FF's each, the one FF that is required to realize this facility would otherwise be present as a dummy. As a remark aside I mention that to only sending a low byte value (thus not followed immediately by a high byte) FF-VIII is not required because A0 is set in the low byte mode by the low level that appears at the Q output of FF-VII due to a low level transfer of FF-III. Some remarks You may have noticed that the values that are send to the interface are not directly converted to an analog value to control the parameter for which it was meant to. Instead they are stored into the memory but, when the refresh action starts it will because all channels are scanned from the memory sequentially between the receiving and the write cycles. This system will only cause a maximum delay of 32 micro seconds before the binary sent value is converted to an analog Voltage to control the parameter. Although not elegant from a pure electronically aesthetic point of view it is effective and saves a lot of extra circuit design. You also may have notice that more than once certain capacitors in context to RC delay networks are drawn stippled. Like already was mentioned in context to the duration of the write pulse these capacitors are not on board components but internal capacities of the chips. The data books for the HCMOS chips determine quite exactly how large this internal capacity is and thus they can be used to function as an element of a RC network. The fact that they do not appear as board components does not mean that they are not important. On the contrary, they are of extreme importance to have the system operating correctly because they generate in combination with the serial resistors the proper delay time of several signals in the system to achieve a proper sequence of events. Write timing diagram The diagram below shows you the timing of a write cycle as a graphic which makes it more easy to understand the system.

 

. . . Read Cycle Requirements The timing diagram above shows you the most important digital signals for the read cycle. When not a byte is received from the computer that need to be stored into the RAM, the interface is continuously reading data from the RAM to refresh the analog memory unit. As was explained before, it was a requirement in the design to refresh all channels of the analog memory at least one time between each byte which the computer sends. When the computer sends its bytes at full MIDI baud rate the following is true: Each byte takes 1000000/31250 baud = 32 micro seconds * 10 bits = 320 micro seconds to be transferred. The start and address byte only initialize the interface (they do not stop the read cycle) and thus The data format: StartByte, AddressByte, HighByte, LowByte and again and again counts 2 different time duration's to read the RAM because it does not need to write a byte. The short one is between the HighByte and the LowByte and counts 320 micro minus the write time of 4 micro (worse case). It is desired to update all 32 channels within 316 micro and thus less than 10 micro per channel is available to read the two bytes from the RAM, transfer them to the DAC registers, convert it to an analog value, to enable the demultiplexer and finally to pump the analog voltage into the memory capacitor. With exception of this last step there is not a physical problem because the digital chips are fast enough. A look ahead on the results To already give you the results of the realized unit; it demultiplexes at a rate of 333KHz. This implies that within 316 micro 105 times a channel can be refreshed. This high speed is quiet unusual for a demultiplexer design (synthesizer designs that often include a multiplexed system like this, mostly demultiplex at a rate of 10 to 20Khz). You might wonder why I choose for this high speed. Actually I was amazed myself that the results were so good. Even stronger: its better than the conventional designs which multiplex at a lower frequency. The first reason to have this higher speed was because I had some future extensions in mind for the V8 unit which requires many extra analog channels to control parameters. To limit the design concept to 128 channels seem to be fair to me. Although there is not a principle need to have all the channels updated between one time interval of the incoming bytes, it seemed a good concept to me because when I started to design I could not oversee all the problems that I would met. In the end, the fact that a refresh cycle of 128 channels does not fit into the time duration between two bytes does not matter with this high speed (as was proved by the specifications that I measured). Data read from RAM Reading the two bytes from RAM together forming a 12 bit binary number to be send to the DAC takes 550ns (nano seconds). This is based on a 200ns Low Power RAM (6116LP-2). The circuitry to read the RAM is dimensioned in such way that all signals are within a save time area for proper operation (think about propagation delays and RC timing tolerance). Digital to Analog conversion The conversion time of the 12 bit DAC (AM6012) including the buffer OpAmp TL072 takes 400ns plus some overshoot recovery time. All together the analog Voltage is stable after 1 micro and the demultiplexer opens the gate for the addressed channel to refresh the Voltage over the memory capacitor. Analog memory The 2 micro seconds time that is available to refresh the capacitor is plenty enough to restore the loss of charge over the capacitor but is not enough to fully charge it when the Voltage needs to change extremely from its lowest (zero Volts) to its highest value (5 Volts). This however is not a problem because in that case it simply will take some extra cycles to fully charge or discharge the capacitor (and you will not notice it). The advantage of high speed demultiplexing A big problem with the demultiplexer IC's like the CD4051 of HC/HCT and also with the integrated CEM5530 are the spikes that appear when channels are switched over in the chip. Secondly the stray capacities on the board also spread the switching spikes all over the place. A big mistakes that is often made by the synthesizer designers is the lack of using the Inhibit pin of the demultiplexer to reduce crossover spikes between the channels. By using the Inhibit possibility properly one can reduce this problem already quite a bit. The demultiplexer must be inhibited before the address change on the chip and made enable again after the address is internally stable. Then the channel in the chip is switched open to charge or discharge the capacitor. When the time has come that a new analog value is about to come the chip must be inhibited again. Last but not least, the very high demultiplexing rate that I used also produce spikes at this rate and thus at a rate of 333Kz and their higher harmonics. These troubling frequencies can be kept out of the audio signal much easier than their 20Khz equivalent from the conventional designs. Even when they are still present you will not hear them because they are far above the limit of our ears. When analog and digital also are grounded properly (like data books advise you to do on this subject) then the system will be extremely silent.

 

. . . DAC and S&H The diagram below shows both the 12 bit DAC and the 32 Sample and Hold channels which store the analog voltage. DAC The two data latches (HC377) receive their data from the RAM memory from the data interface. The interface also generates a HB and LB strobe to transfer the two bytes, which appear after each other on the bus, into a 12 bit wide data register to the DAC. The DAC converts it into a current and the OpAmp converts it into a positive Voltage within the range of 0 to 5 Volts. S&H The Analog voltage from the DAC is multiplexed. On a high speed the interface reads the memory for 128 channels and send the binary values to the DAC. The Analog Voltage from the DAC then need to be demultiplexed and stored into a hold capacitor to be memorized. The CEM 5530 chip is a complete demultiplexer and S&H chip. It includes on chip hold capacitors but, it only has 30 channels. The two missing channels which are required to control the Voices are therefore build up with a CD4051 and TL072. The other channels that are read from RAM do not exist yet. The address and inhibit lines of both the CEM and CD4051 are controlled by the data interface which sends the corresponding address of the RAM location which it reads. Because the CEM has 30 channels instead of 32, the addressing is a bit more complicated than it would be when the CEM had 32 channels. Now the CEM needs to inhibited when channel 30 and 31 need to be controlled and the CD4051 need to be inhibited when any channel below number 30 is activated. If you draw back to the interface diagram, you can see that the address decoder has some extra logic to achieve this unhandy address method. The 32 analog voltages from the S&H unit are connected to the 8 voices to control each of the four parameters of the voice (Filter frequency and Resonance, Amplitude and Balance).

 

. . . VOICES The CEM3389 chip This chip, especially designed for synthesizers, has all the circuitry integrated for a Voltage Controlled 24dB low pass filter with Frequency and Resonance control, a Voltage Controlled Amplifier and a Voltage Controlled stereo output Balance stage. To make the chip operational as a Voice end stage only some components are required to interface the chip to the control voltages, to adjust the scaling and to set some initial parameters. Because I used the board from my CTS2000 keyboard I only needed to modify a little to improve the specifications of the board and adapt it for my purpose. I upgraded some components, decreased the input impedance to gain a better S/N ratio. Furthermore it is right now not much of a use to go deeper into the inner world of the chip because it is used as a black box without the possibility to change much about it by changing the surrounding components. If you do want to know more about the chip, you have to study the data books of the manufacturer. By the way: the CEM (Curtis) synthesizer chips are not in production anymore. The rumor goes that you can let any CEM chip to be produced for you when you order some thousands of them (Ha! what an art). A remarkable fact of the CEM chip is its possibility to oscillate. When the resonance is put at its maximum it starts to produce a sine wave that is frequency controllable and thus the circuitry becomes a VCO. Because of its 12 bit control resolution the VCO can be tuned precisely.

 

. . . Power Supply The diagram below shows the power supply for the V8 unit. It is a straight forward design with the popular 78xx and 79xx regulators. The supply delivers 3 regulated voltages for both the positive and negative supply. The only remarkable detail you may notice is the capacitor in series with the primary winding of the transformer. The transformer that is used has quite a higher secondary Voltage than specified under full load conditions and because it is not fully ballasted by the V8 unit, this secondary voltage much is higher than required. The capacitor decreases the secondary voltage to a level that is more suitable. Because the V8 uses a quite static current flow the solution with the capacitor works perfect. The value is dimensioned to give 20 Volts after the rectifier and thus also has enough head room to prevent the unregulated Voltage become too low due to variations of the 220V line input. The capacitor also gives the advantage that the transformer operates below its maximum capacities and therefore dispenses less power and less magnetic radiation.

For response see Marc Marc contact file This page and all contents: (C)1996 by Marc Marc Amsterdam Back to Sound Mover block diagram